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What to do if firmware disables SWD pins? Help!

John Beans

So, we've messed up and loaded firmware onto Apollo 2 that reassigns/disables the SWD pins 20,21. Since SWD is our only programming interface on the board, we can no longer erase/program the part.

Does anyone know of a tool that can erase Apollo 2 over the SWD pins when this happens? Maybe something that can execute extra-fast to beat the pin configuration commands after reset? 

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Comments

2 comments

Date Votes
  • Andre Belanger

    John,

    I responded yesterday morning to the support ticket you submitted with this same question.   If you need further clarification on the recovery method I recommended, please submit your question to that ticket.

    In case you are having trouble accessing the support system, I will repeat the recovery method here.  This recovery method may also be helpful to others that run into this same issue.

     

    Recovering a device where the SWD pins are being reconfigured to other function by software.

    It is usually possible to recover from this, with the level of difficulty being determined by how soon after reset your code is disabling the SWD pins.

    This recovery method uses J-Link debugger, so for an Apollo2 EVB you can use the built-in debug conection and for a different target board you can use an Apollo2 EVB as debug adapter, cabling from its DEBUG OUT connector from the EVB over to your target board.  The idea is to quickly halt code execution before any of your application code is run (so before the SWD pins are disabled).

    Recovery method uses the J-Link command-line debugger interface.The J-Link Commander console software is included in the standard Segger J-Link software package.

    Here are instructions that work for J-Link Commander command-line interface with J-Link debugger:
    1. Power-down Apollo completely  (to get all registers to default value)
    2. Hold Apollo nRST low (to prevent code from executing)
    3. Power-up Apollo while continuing to hold nRST low
    4. Use Segger J-link commander console to connect to Apollo (should connect even though nRST is asserted, but cannot program/erase while nRST is asserted)
    5. Type a long list of “halt” commands into a text editor, copy them into clipboard, then paste into the J-Link command window.  The halt commands that try to execute while nRST is held low will fail, and will execute quickly, so you need to paste a long list of halt commands (~ 100)
    6. Immediately release nRST while the halt commands are being processed (note that even 100 halt commands will execute in ~ 1 second so small but manageable window in which to release nRST)
    7. Debugger should reports that halt was successful, at which point the erase command can be used to remove the problem firmware from the Apollo.
    8. If the halt commands fail, then the full procedure should be repeated starting from step #1 (simply asserting reset will not be sufficient for many issues, need to start from power-down).

    JLink Commander: 
    The J-Link can also be controlled by a command line interface. Here is an example of using the J-Link Commander command line interface to connect to an Apollo2 (same will work for Apollo2Blue):
    Type "connect" to establish a target connection, '?' for help
    J-Link>connect
    Please specify device / core. <Default>: AMAPH1KK-KBR
    Type '?' for selection dialog
    Device>AMAPH1KK-KBR
    Please specify target interface:
      J) JTAG (Default)
      S) SWD
    TIF>S
    Specify target interface speed [kHz]. <Default>: 4000 kHz
    Speed>1000
    Device "AMAPH1KK-KBR" selected.

    Connecting to target via SWD
    Found SW-DP with ID 0x2BA01477
    Scanning AP map to find all available APs
    AP[1]: Stopped AP scan as end of AP map has been reached
    AP[0]: AHB-AP (IDR: 0x24770011)
    Iterating through AP map to find AHB-AP to use
    AP[0]: Core found
    AP[0]: AHB-AP ROM base: 0xE00FF000
    CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
    Found Cortex-M4 r0p1, Little endian.
    FPUnit: 6 code (BP) slots and 2 literal slots
    CoreSight components:
    ROMTbl[0] @ E00FF000
    ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS
    ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 003BB002 DWT
    ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 002BB003 FPB
    ROMTbl[0][3]: E0000000, CID: B105E00D, PID: 003BB001 ITM
    ROMTbl[0][4]: E0040000, CID: B105900D, PID: 000BB9A1 TPIU
    Cortex-M4 identified.
    J-Link>erase
    Erasing device (AMAPH1KK-KBR)...
    J-Link: Flash download: Total time needed: 2.035s (Prepare: 0.065s, Compare: 0.000s, Erase: 1.966s, Program: 0.000s, Verify: 0.000s, Restore: 0.004s)
    Erasing done.
    J-Link>

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  • Andre Belanger

    The large amount of halts that you paste into the J-Link commader window immediately befopre releasng reset should be at least 100 long and look something like the following.  You should copy the full list into clipboard then paste into the commander console as described in above steps.

     

    halt
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