In the MCU Core Details chapter of the Apollo2 Datasheet, the PWRCTRL_MISCOPT register in the Power Control section enables setting of two bit fields, DIS_LDOLP-MODE_TIMERS and DIS_LDOLP-MODE_HFRC. Why are these fields cleared (disabled) by default? When should I set these bits?
As stated in the Description field for these bits, Setting the DIS_LDOLPMODE_TIMERS bit enables the MEM LDO to be in LPMODE during Deep Sleep Mode even when the ctimers or stimers are running. Setting the DIS_LDOLPMODE_HFRC bit enables the Core LDO to be in LPMODE during Deep Sleep Mode even when HFRC is enabled.
We recommend setting the DIS_LDOLP-MODE_TIMERS bit if timers are running in Deep Sleep Mode, but no timers are using HFRC as count source. If timers are running from HFRC, this bit should be cleared. The AmbiqSuite's Apollo2 HAL automatically checks if timers are using HFRC and sets or clears this bit in am_hal_ctimer_config, am_hal_ctimer_config_single, and am_hal_stimer_config timer configuration functions.