Apollo MCU's have multiple peripheral modules for serial master communication to SPI and I2C. One instance of this peripheral module is called an IOM or I/O Master. Apollo1 has 2 IOM's and Apollo2 has 6.
Each IOM is configured via the following registers:
- CFG Register - Bitfields select SPI/I2C, and other characteristics of the communication for the IOM
- INTEN Register - Bits enable specific interrupts for the IOM, such as THR which is mentioned later.
Every transaction utilizes the following architectural features of the IOM module:
- CMD Register - Several bits and bit fields set the operating mode of the controller for the IOM module.
- Internal 128-bit FIFO - holds transmit and receive data as the IOM controller arbitrates the transaction
Below are some excerpts from the Apollo2 datasheet pertaining to CMD register fields:
Note that OPER, OFFSET, and LENGTH fields are utilized for both I2C and SPI operation.
Following are explanations of these fields:
OPER - A normal read or write will pre-pend register address information and set address via an initial write. A raw read or write will simply write or read LENGTH bytes of data with no special
OFFSET - This contains the pre-pended address for I2C or SPI operation when a normal OPER mode is selected.
LENGTH - This specifies the number of data bytes to read or write via the 128-byte FIFO. It is possible that more bytes will be transferred. This is especially true for SPI, which contains the UPLNGTH field to extend length up to 4095 bytes. When more than 128 bytes will be written, it will be necessary to utilize FIFO interrupts to move the FIFO data to a buffer in RAM periodically.
The internal 128-byte FIFO is accessed as 32-bit (4 byte) words. This means the FIFO is 32 words in length. Here are some registers of note pertaining to FIFO operation, explained in greater detail in the Apollo2 datasheet:
- FIFO Register - transfers to/from FIFO are performed a word at a time via this register
- FIFOPTR Register - Contains the count of bytes taken and bytes remaining in the FIFO
- FIFOTHR Register - Contains write and read threshold settings at which threshold interrupts for the IOM will trigger. The ISR for the threshold interrupt should write/read the FIFO Register.
AmbiqSuite SDK (HAL / BSP)
The functionality for each IOM is encapsulated in the AmbiqSuite SDK HAL. Pin assignments for each IOM are made in the BSP (via am_bsp_gpio.h).